1. Field of the Invention
The present invention relates to a circuit for a primary-side controlled power converter, and more particular to an adaptive filter circuit for a primary-side controlled power converter.
2. Description of the Prior Art
FIG. 1 shows a schematic circuit of a conventional primary-side controlled power converter. The primary-side controlled power converter comprises a transformer 10 including a primary winding NP, a secondary winding NS, and an auxiliary winding NA. An input voltage VIN of the power converter is supplied to the primary winding NP. A switching controller 100 is coupled to a voltage divider formed by resistors 51 and 57 and samples a reflected voltage VA of the auxiliary winding NA of the transformer 10 through the voltage divider. One terminal of the resistor 51 is connected to the auxiliary winding NA of the transformer 10, and the other terminal of the resistor 51 is connected to one terminal of the resistor 57. The other terminal of the resistor 57 is coupled to ground. The resistor 51 is connected to the resistor 57 in series. Based on the reflected voltage VA, a signal VS is generated at the join of the resistor 51 and the resistor 57 and applied to a detection terminal VS of the switching controller 100. The reflected voltage VA and the signal VS are correlated to an output voltage VO of the power converter. The primary-side controlled power converter further comprises a rectifier 40 and a capacitor 45. An anode of the rectifier 40 is connected to the resistor 51 and the auxiliary winding NA. A cathode of the rectifier 40 is connected to the capacitor 45. A supply voltage VCC is supplied to a supply terminal VCC of the switching controller 100, which is connected to a join of the cathode of the rectifier 40 and the capacitor 45. An anode of a rectifier 60 is connected to the secondary winding NS of the transformer 10, and a cathode of the rectifier 60 is connected to an output capacitor 65. A load 70 is connected to the output capacitor 65 in parallel, and the output voltage VO is generated at one terminal of the load 70.
The switching controller 100 receives the signal VS which can be regarded as a voltage feedback signal correlated to the output voltage VO of the power converter. In responsive to the voltage feedback signal, the switching controller 100 generates a switching signal SW to switch a power transistor 20 and the transformer 10, so as to regulate the output voltage VO of the power converter. When the switching signal SW becomes logic-high, a primary-side switching current IP will be generated accordingly. A current-sense resistor 30 coupled to the power transistor 20 can serve as a current-sense device. A current-sense signal VCS is generated at a join of the current-sense resistor 30 and the transistor 20, and applied to a sense terminal CS of the switching controller 100. The detailed description of the primary-side controlled power converter can be found in the following: U.S. Pat. No. 6,977,824, entitled “Control circuit for controlling output current at the primary side of a power converter”, and U.S. Pat. No. 7,016,204, entitled “Close-loop PWM controller for primary-side controlled power converters”.
The waveform of the signal VS is schematically shown in FIG. 2. The signal VS is generated during the off-time period of the switching signal SW. After a blanking period TBLK elapses, the signal VS can be stable and related to the output voltage VO. However, the leakage inductance of the transformer 10 and the drain capacitance of the power transistor 20 cause a ringing signal VRING with a ringing period TRING in the signal VS. In addition, the reflected voltage VA includes the ringing signal VRING due to the voltage divider, which causes undesired values in the signal VS.
FIG. 3 shows another schematic circuit of a conventional primary-side controlled power converter. A capacitor 58 is connected to the join of the resistors 51 and 57 and ground so as to reduce the ringing signal VRING in the signal VS. The resistors 51 and 57 and the capacitor 58 develop a low-pass filter. However, the low-pass filter causes distortion and sample errors of the signal VS. FIG. 4 shows the distorted waveform of the signal VS during the off-time period of the switching signal SW. Because of the low-pass filter, the waveform of the signal VS is distorted and the rising time of the signal VS is prolonged, which causes sampling errors when the pulse width of the signal VS is short. For example, when the load is in a light-load or no-load condition, the pulse width of the signal VS is too short to be accurately sampled by the controller 100 for generating the voltage feedback signal because of the small pulse width of the switching signal SW. Sample errors result in an incorrect voltage feedback signal (lower value of the voltage feedback signal) and cause an increment in the output voltage VO. In other words, the output voltage VO will be too high because the controller 100 senses an incorrect voltage feedback signal. Furthermore, the distorted waveform and the prolonged settling-time period TD of the signal VS limit the maximum speed and the maximum frequency of the switching signal SW.